This application claims priority to Chinese Patent Application No. 200910056517.1,filed Aug. 13, 2009, entitled “A Method and Structure for Self Aligned Contact for Integrated Circuits,” by inventors ChiKang Liu, ZhengYing Wei, GuoXu Zhao, YangFeng Li, GuoLiang Zhu, and FangYu Yang, commonly assigned, incorporated by reference herein for all purposes.
Embodiments of the present invention are directed integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, embodiments of the invention provide a method and system for forming a self aligned contact for a high voltage semiconductor integrated circuit device. But it would be recognized that the invention has a much broader range of applicability. For example, the invention can be applied to a variety of other applications such as application specific integrated circuits, microprocessors, and memory devices.
Over the past decades, integrated circuits have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Performance and complexity are far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of integrated circuits. Certain semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of circuits but also provided lower costs to consumers. Conventional semiconductor fabrication plants often costs hundreds of millions or even billions of U.S. dollars to construct. Each fabrication facility has a certain capacity measured in tens of thousands of wafer starts per month. Each wafer also has a certain number of potential chips. By manufacturing individual devices smaller and smaller, more devices are packed in a given area of semiconductor, which increases output of the fabrication facility. Making devices smaller is always very challenging, as each process for the manufacture of semiconductor devices has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout should be changed.
Costs of operating fabrication facilities have also increased dramatically. As many know, many U.S. fabrication facilities that were operable in the 1970's and 1980's no longer exist. Many of such fabrication facilities migrated to Japan in the 1980's and then to Korea and Taiwan in the 1990's. As demand for lower cost fabrication facilities continues, China has now become a choice geographic location for fabrication facilities to start up. Many companies have announced plans to begin manufacturing facilities in China. Such companies include, but are not limited to, Motorola, Inc., Taiwan Semiconductor Manufacturing Corporation of Taiwan, also called TSMC, and others. Although labor costs may be somewhat lower in China, there are still many costs that still need to be reduced or even eliminated as the demand for lower cost silicon continues!
An example of a process that has limitations based upon a given feature size is the formation of contact structures for a high voltage semiconductor device. Such contact structures include an opening that traverses through a thickness of dielectric material to an active region of the high voltage device. The active region is often a source/drain region of a specialized MOS transistor, which serves as the high voltage device. The opening, however, is often difficult to align accurately, which leads to a voltage breakdown for the specialized MOS transistor. These and other limitations of the conventional high voltage semiconductor device can be found throughout the present specification and more particularly below.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.